In conventional semiconductor processing, circuit elements are created on a wafer by exposing photosensitive materials on the wafer with a pattern of transparent and opaque features on a mask or reticle. The selectively exposed areas of the photosensitive materials can then be further processed to create the circuit elements. As the size of the circuit elements to be created on the wafer becomes similar to, or smaller than, the wavelength of light or radiation that illuminates the mask, optical distortions can occur that adversely affect the performance of the circuit. To improve the resolution of the photolithographic process, many circuit design programs utilize one or more resolution enhancement techniques (RETs) that attempt to compensate for the expected optical distortion such that the mask patterns will be printed correctly on the wafer.
It is well known that one factor in determining how well a pattern of features on a mask will print is the pattern of light or radiation that illuminates the mask. Certain types or orientations of features on a mask will print with better fidelity when exposed with a particular illumination pattern. For example, off-axis illumination has been used in microlithography for projection printing since the late 1980s because it increases resolution and depth of focus for certain layout patterns and design styles. Due to the demand to resolve smaller and smaller images, the deployment of a variety of off-axis illumination source shapes was developed: first annular, then quadrapole, and lately dipole. These illumination source shapes can be formed by hard stop apertures or by diffractive optical elements (DOE). The latter is advantageous because it preserves light energy on the way from a laser source to the mask (object) resulting in less throughput loss. In addition, DOEs can form very complex source shapes, with a smooth distribution of light across the aperture. This enables source tuning to print certain layout features with high resolution. Although lithographic exposure equipment is compatible with the use of more complex illumination shapes, there has been no technique to reliably determine a practical optimum illumination pattern for a given layout pattern, and in particular for that layout pattern once RETs have been applied. Therefore, there is a need for a method of determining what illumination pattern should be used for a particular pattern of features to be printed on a wafer.